DesignCon 2022 Schedule Builder

Power integrity engineers understand how parasitic path inductance combined with fast di/dt load transients can lead to excessive voltage ripple. This leads to the concept of target impedance to ensure that the dynamic current times the impedance will not exceed a maximum allowed power rail ripple. The concept is simple. But what does a designer do when device data sheets do not provide dynamic current information? The answer depends on what fidelity of solution is needed and what one can afford either in schedule or monetary risk. This paper compares multiple methods and levels of fidelity to determine the dynamic current required for calculating target Z for a PDN design.

Methods to accurately determine dynamic load current range from the overly simplified 50% of max power step load to massive transistor level simulations or extreme measurements. However, it is important to remember that a target Z based solely on the load's di/dt would leave zero margin for other noise sources such as external transients, switching noise, and EMI. This paper takes a deep dive into the different methods of calculating target Z for a high speed SERDES power rail while also including additional margin to account for multiple noise sources.

Takeaway

Power integrity engineers use target impedance to optimize the delivery of power to the load, but when data sheets fail to provide a complete picture of target Z vs. frequency the PI engineer must find methods to calculate this on their own.

Intended Audience

No prerequisites required, but recommend some familiarity with power integrity target Z and s-parameter PDN models.