DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.


Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Prediction of Power Supply Induced Jitter in DDR Interfaces

Licheng Wu (Hardware Systems Engineer, NXP Semiconductors)

Location: Ballroom A

Date: Wednesday, January 29

Time: 11:00am - 11:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

This paper proposes a method to analyze and predict the power supply induced jitter (PSIJ) on data eye caused by both PHY core supply and I/O supply in a DDR interface. Apart from predicting power supply induced edge TIE jitter of an individual data signal using extracted jitter sensitivity and power noise profile, the impact of jitter tracking effect and edge slope modulation on final data eye jitter is also considered by developing an analytical model. The accuracy of predicted data eye jitter is verified by measurements in an LPDDR4-3000 interface. An overall error of less than 20% is observed.

Takeaway

A method to predict power supply induced data eye jitter in DDR interfaces, which considers the impact of jitter tracking and edge slope modulation, allowing the predicted jitter number to be directly used in DDR interface timing calculation.