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Prepare for DDR5 Test Challenges as We Migrate to Next Gen Memory

Saifee Jadanswala  (Memory Solution Marketing Engineer, Tektronix)

Location: Room 203

Date: Thursday, January 30

Time: 11:05am - 11:45am

Track: Sponsored Session

Vault Recording: TBD


With the robust list of new features, DDR5 SDRAM pushes the limits of high-speed signaling and tackles the memory bandwidth challenge caused by the exponential growth in data generated by cloud computing, IoT and real-time data analytics, and addresses the need of data centers to continuously store, transfer and process that data faster. DDR5 brings in unique test challenges which were never before seen in the memory world. This presentation will provide an update on the DDR5 Rx/Tx compliance test and provide insight in the latest characterization and debug techniques to enable analysis of the highest DDR5 speed grades.