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Amanda (Xiaoqing) Dong (SerDes design engineer, Xilinx)
Bi Yi (SI design engineer, ZTE)
Nick (Chunxing) Huang (SI design engineer, Shenzhen Zhongzeling Electronics)
Geoff (Geoffrey) Zhang (Distinguished Engineer, ,Xilinx)
Location: Ballroom G
Date: Wednesday, January 29
Time: 11:00am - 11:45am
Track: 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC), 09. High-Speed Signal Processing, Equalization & Coding
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
In addition to DFE burst errors, QPRBS31 is identified as another major source of correlated errors in 56G+ PAM4 systems. Analysis of QPRBS31 polynomial reveals the attenuation and repetition rules of worst-case ISI patterns whose maximum occurrence probability in an RS-FEC frame is around 1e-5~1e-6, where FER simulation was observed to diverge from measurement. This paper introduces a worst-case ISI pattern construction method and based on which a two-step FEC SG simulation method are introduced. Probabilities of all FEC errored symbol patterns under random and correlated input errors are combined for FER analysis. Examples are given and show good correlation.
QPRBS31 is proved to be a major source of correlated errors in 56G+ PAM4 systems. To model the correlated error impact and to close the gap between simulation and measurement, a worst-case ISI pattern construction method and a two-step FEC SG simulation method are introduced. Examples given show good correlation.