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Thomas To (Technical Director, Xilinix)
Ajay Kumar Sharma (Senior Manager, Xilinx)
Nitin Srivastava (Staff SI Engineer, Xilinx)
Changyi Su (Senior Signal and Power Integrity Engineer, Xilinx)
Ed Priest (Distinguished Engineer, Device Power and Signal Integrity, Xilinx)
Juan Wang (Signal Integrity Engineer, Xilinx)
Location: Ballroom B
Date: Thursday, January 30
Time: 2:50pm - 3:30pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Many Advanced Computing System-on-Chip (SOC) implement special computing elements such as Artificial Intelligent Engine (AIE) to support AI Machine Learning (ML) Applications. Because ML applications are still evolving, the power and thermal conditions of the ML computing SOC is not clearly understood. This paper will show a System Monitor (Sys Mon) that can monitor the on-die conditions when different ML applications are used when pairing up with DDR4 and LPDDR4 system memory. The monitored voltage will be compared to direct voltage probing results. The knowledge obtained can be applied to optimize between system requirements and physical system conditions.
Understanding of the real time on-die condition is critical especially for advanced computing platform such as in machine learning applications. This paper presents the system monitor to facilitate real time on-die measurement. Different usage comparisons allow system designers to trade off between system requirement and physical conditions.