April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Speaker:
Marianne Nourzad (Analog Engineer, Intel)
Authors:
Hsinho Wu (Design Engineer, Intel)
Christiaan Bil (Analog Engineer, Intel)
Joseph Boon Hock (product development engineer, Intel)
Masachi Shimanouchi (Design Engineer, Intel)
Karsten Stangel (Analog Engineer, Intel)
Jong-Ru Guo (Analog Engineer, Intel)
Mohiuddin Mazumder (Senior Principal Engineer, Intel)
Zuoguo Wu (Senior Principal Engineer, Intel)
Mike Li (Fellow, Intel)
Location: Ballroom G
Date: Wednesday, April 6
Time: 11:15 am - 12:00 pm
Track: 12. Applying Test & Measurement Methodology, 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
This paper will provide a detailed overview and comparison of the methods used for the calibration and receiver testing for PCI-Express 6.0 and IEEE 802.3 Ethernet. Starting with PCIe 6.0, PAM-4 signaling scheme is used for PCIe, as opposed to Non-Return to Zero (NRZ) signaling for previous PCIe generations. As a result, significant changes in calibration tools and measurement capabilities are needed for PCIe 6.0 Receiver testing. A methodology comparison to the already established IEEE 802.3 Ethernet is done both theoretically and by observing the Bit Error Rate impact on commercially available silicon, while subjecting the Receiver under test to both PCIe stressed eye calibration and IEEE interference tolerance calibration recipe.
The audience will gain the knowledge on receiver calibration and testing in PAM-4 high-speed serial links, including the upcoming PCI-Express 6.0 receiver stressed eye calibration methodology.
For audience with knowledge on high-speed serial links, jitter and noise components, and receiver calibration and testing schemes in serial communication links