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Reduce Simulation Complexity in DDR4 and Get Ready for DDR5

Stephen Slater (High-Speed Digital Simulation Product Manager, Keysight Technologies)

Location: Great America 1

Date: Thursday, January 31

Time: 11:05am - 11:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Audience Level: Intermediate

Keysight Technologies

The insatiable desire for more bandwidth in data centers has led to intense pressure to push DDR5 memory technology out to market faster. Eagerly anticipated to release in 2019, DDR5 is expected to have twice the data rate of DDR4. For high-speed PCB designs, both DDR4 and DDR5 are not without challenges and significant risks as design margins shrink quickly. During this webinar you will learn how to cut through the complexity of setting up simulations for DDR. We’ll show you how to approach a practical design and analysis workflow for DDR4, and ready yourself for DDR5. Furthermore, you will better understand the simulation and modeling eco-system and how compliance measurements can be used to deliver a more predictable design flow and reduce time-to-market.
Key Learnings:
1. Learn how to cut through simulation complexity
2. Gain an understanding of design challenges and the IBIS-AMI modeling eco-system
3. Learn how to use simulation tools to prepare yourself for DDR5 designs now