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Mike Li (Fellow, Intel)
Hsinho Wu (Design engineer , Intel)
Masashi Shimanouchi (Design Engineer , Intel)
Location: Ballroom A
Date: Wednesday, January 29
Time: 9:00am - 9:45am
Track: 09. High-Speed Signal Processing, Equalization & Coding, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
This paper focuses on the latest OIF/CEI (112G) and Ethernet (106G) VSR chip-to-module (C2M) electrical interfaces. Specifically, we will present the use of COM for the host and module output specifications and compare them with the nominal time-domain simulation method/tool, and highlight the difference and how to reconcile. We then use the correlated COM, with various reference receivers, to do a large volume simulations on the host/module signal outputs, over a range of host/module packages and channels. We further discuss how the specification could be defined/improved based on the new simulation results.
This paper focuses on the latest OIF/CEI (112G) and Ethernet (106G) VSR chip-to-module (C2M) electrical interfaces. Specifically, we will present the use of COM for the host and module output specifications and compare them with the nominal time-domain simulation method/tool, and highlight the difference and how to reconcile. We then use the correlated COM, with various reference receivers, to do a large volume simulations on the host/module signal outputs, over a range of host/module packages and channels. We further discuss how the specification could be defined/improved based on the new simulation results.
For audience with knowledge on high-speed serial links, jitter and noise components, and equalization schemes in serial communication links.