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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Steve Krooswyk (Sr SI design engineer, Samtec)
Beomtaek Lee (Senior Principal Engineer, Intel)
Hansel Dsilva (Senior Staff Signal Integrity Engineer, Achronix Semiconductor)
Richard Mellitz (Distinguished Engineer, Samtec)
Adam Gregory (Signal Integrity Engineer , Samtec)
Stephen Hall (Senior Principal Engineer , Intel)
Location: Ballroom D
Date: Thursday, April 7
Time: 12:15 pm - 1:00 pm
Track: 07. Optimizing High-Speed Link Design, 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER
Format: Technical Session
Theme : Data Centers, High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
Today's high speed interfaces are ever increasingly sensitive to reflections, leading to pressure to characterize and supress channel and component discontinuities. Differentiation in characterization methods is high between standards such as PCIe, IEEE 802.3 and USB, and we are sometimes confused when we approach these standards. To aid, this paper explains each reflection standard, their history, use of parameters, and applications. Then, we evaluate their correlation to what matters most: end-to-end channel margins at 32 GB/s NRZ and 112 GB/s PAM4. Included standards are RL, IMR, ILD, IRL, and ERL, along with new unadopted metrics of RILN and iRL.
Comparing of the different reflection metrics which include return loss mask, integrated multi-reflections (IMR), integrated return loss (IRL), figure of merit of insertion loss deviation (FOM_ILD) and effective return loss (ERL). Results presenting the effectiveness of the different reflection metrics in tracking the amount of reflections leading to degradation in margin.