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Reflection Cancellation Design with Embedded Resistor for DDR Memory System

Yang Wu (SI Enginner, Intel)

Maoxin Yin (SI Engineer, Intel)

Jun Ye (Test R&D Engineer , Intel)

Tao Xu (Engineering Manager, Intel)

Location: Ballroom A

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 05. Advances in Materials & Processing for PCBs, Modules & Packages

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

An innovative design is proposed in this paper to address the multi-load DDR command/ address/ control (CAC) signals' reflection problem without requiring additional layout spacing. In this design series resistors are inserted in the memory chip branches of the fly-by topology, which cancel the reflection in one direction. These resistors are implemented by embedded resistor technology to break the limitation of layout spacing. The simulation and validation results show this design can effectively optimize the margin of the CAC signals and help system to achieve higher operation speed.


A reflection cancellation design with series resistors for DDR control/address/command signal fly-by topology is implemented by embedded resistor technology. The simulation and validation results show this design can effectively optimize the signal quality and margin of the DDR control/address/command signals.

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