April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Risks & Enablers of Server Platform Design in Immersion Cooling
Speaker:
Shaohua Li (Analog engineer, Intel)
Authors:
Dan Liu (Staff Engineer of Signal Integrity, Alibaba)
Yangfan Zhong (Senior Staff Engineer, Alibaba)
Honghao Cao (Staff Engineer, Alibaba)
Yunhui Chu (Signal Integrity Engineer, Intel)
Kai Wang (Signal Integrity Engineer, Intel)
Haifeng Gong (Principal Engineer, Intel)
Tina Bao (Signal Integrity Engineer, Intel)
Location: Chiphead Theater
Date: Thursday, April 7
Time: 4:40 pm - 5:00 pm
Track: Chiphead Theater, 13. Modeling & Analysis of Interconnects
Format: Lightning Talk
Theme : Data Centers, Infrastructure
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
Immersion Cooling is emerging in many data center and edge applications, while it brings huge performance and energy efficiency benefits to datacenter and IT equipment owners, it also introduces new signal integrity challenges to high-speed buses designed for air cooling but used for immersion cooling. This paper investigates risks of immersion cooling on DDR4/DDR5 interfaces and high-speed differential IO PCIe Gen5. A solution to improve eye margin degradation caused by cooling medium change is proposed. The solution is an efficient and low-cost way to enable immersion cooling application on data center platform.
Takeaway
Immersion cooling can impact impedance matching and crosstalk. For DDR4 and DDR5, impact on signal from cooling medium change can be acceptable. For PCIe Gen5 at 32Gb/s, signal degradation from cooling medium change is obvious. A solution is proposed to enable the immersion cooling on PCIe Gen5 platform.
