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Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Danny Ho  (SI/PI Department Manager, Media Tek)

Location: Mission City M1

Date: Thursday, January 30

Time: 11:05am - 11:45am

Track: Sponsored Session

Vault Recording: TBD

Cadence Dseign Systems

Nowadays, the high-speed SerDes on 2.5D IC integration design is extensively applied on applications such as networking and artificial intelligence for data center communications, and the whole channel of high-speed SerDes (up to 112Gbps) has become highly valued for signal integrity performance, especially, modeling methodology is the fundamental and key point. In this paper, the 2.5D channel SI effect including impedance mismatch due to increased C-load effect as well as cross coupling effect from very closed bump structure were evaluated to find out if any SI performance impact. Therefore, 3D-FEM channel model extractor plays a critical role in this analysis. Upon this basis, the extraction of the wafer-level signal path was proposed and also took whole channel of full wave extraction into consideration. The results indicated some impacts by these effects not only in time domain performance, but also in frequency domain of each SerDes block. Last but not the least, the model extraction of computation resources and cost also are shown.