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Ashkan Hashemi (SoC Design Engineer, Intel Corporation)
Guang Chen (SoC Design Engineer, Intel Corporation)
Hyosoon Kang (SoC Design Engineer, Intel Corporation)
Wendem Beyene (Principal Engineer, Intel Corporation)
Location: Ballroom A
Date: Thursday, January 30
Time: 11:00am - 11:45am
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 13. Modeling & Analysis of Interconnects
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
Heterogeneous packaging techniques are critical to enable high-density I/O communication between two or multiple chips. In this paper, Intel's embedded multi-die interconnect bridge (EMIB) solution has been utilized to realize ASIC fabric-to-fabric connection. A comprehensive layout-based signal and power integrity co-simulation methodology is presented for the interface between the ASIC cores. The link analysis characterizes channel's ISI, crosstalk as well as SSN separately, also the on-die signal models have been extracted and correlated. At the end, transient eye diagrams are generated to verify the interface compliance.
In this paper, channel model of a new high-density die-to-die EMIB-based multi-die design has been extracted and correlated. The resulting models were then incorporated in full channel co-simulation methodology to capture ISI, crosstalk, and SSN effects simultaneously. The resulting transient eye diagrams verified the compliance of the interface.