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Simulation & Measurement Correlation of Power Supply Noise Induced Jitter for Core & Digital IP Blocks

Hyo-Soon Kang (SI/PI Engineer, Intel Corporation)

Guang Chen (Sr. SI/PI Engineer, Intel)

Ashkan Hashemi (SI/PI Engineer, Intel Corporation)

Wern Shin Choo (Electrical Validation Engineer, Intel Corporation)

Wendem Beyene (Principal Engineer, Intel Corporation)

David Greenhill (Author, Intel)

Location: Ballroom E

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 11. Power Integrity in Power Distribution Networks

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Introductory

Power supply noise induced jitter (PSIJ) is one of the major sources of timing uncertainties in high-speed electronic systems. The PSIJ analysis methodology for core and IP digital blocks is developed using the frequency-dependent jitter transfer function. We correlate the PSIJ analysis results with measurements in which clock and data paths are designed in FPGA chips. The jitter sensitivity is verified with delay measurement at different voltages. With the integration of the device core operation, power supply noise is generated, and the induced jitter is measured. By changing the noise frequency, we correlated the frequency-dependent jitter transfer function with measurements.

Takeaway

Simulation and measurement correlation of power supply noise induced jitter (PSIJ) is demonstrated. The input and output of analysis such as circuit delay/sensitivity and noise profile, frequency-dependent jitter transfer function and the induced jitter are compared with the measurements.

Presentation Files

PAPER_01_SimulationMeasurementCorrelationOf_Kang.pdf
SLIDES_01_SimulationMeasurementCorrelationOf_Kang.pdf