DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Simulation & Measurement Correlation of Power Supply Noise Induced Jitter for Core & Digital IP Blocks

Hyo-Soon Kang (SI/PI Engineer, Intel Corporation)

Guang Chen (Sr. SI/PI Engineer, Intel)

Ashkan Hashemi (SI/PI Engineer, Intel Corporation)

Wern Shin Choo (Electrical Validation Engineer, Intel Corporation)

Wendem Beyene (Principal Engineer, Intel Corporation)

David Greenhill (Author, Intel)

Location: Ballroom E

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 11. Power Integrity in Power Distribution Networks

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Introductory

Power supply noise induced jitter (PSIJ) is one of the major sources of timing uncertainties in high-speed electronic systems. The PSIJ analysis methodology for core and IP digital blocks is developed using the frequency-dependent jitter transfer function. We correlate the PSIJ analysis results with measurements in which clock and data paths are designed in FPGA chips. The jitter sensitivity is verified with delay measurement at different voltages. With the integration of the device core operation, power supply noise is generated, and the induced jitter is measured. By changing the noise frequency, we correlated the frequency-dependent jitter transfer function with measurements.


Simulation and measurement correlation of power supply noise induced jitter (PSIJ) is demonstrated. The input and output of analysis such as circuit delay/sensitivity and noise profile, frequency-dependent jitter transfer function and the induced jitter are compared with the measurements.

Presentation Files