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HYO-SOON KANG (SI/PI Engineer, Intel Corporation)
Wendem Beyene (SI/PI Manager, Intel Corporation)
Ling Yu (SoC Design Engineer, Intel Corporation)
Location: Ballroom C
Date: Wednesday, January 29
Time: 11:00am - 11:45am
Track: 02. Chip I/O & Power Modeling & Validation Solutions, 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Introductory
Power supply noise induced jitter (PSIJ) is one of the major sources of timing uncertainties in high-speed electronic systems. To analyze PSIJ, empirical methodologies in frequency and time domains are developed using the DC delay sensitivity (ps/mV) of key circuit blocks individually. In this paper, we examined the PSIJ results of empirical approaches by comparing transistor-based SPICE simulations of complete high-speed data and clock paths such as clock tree, phase interpolator, mux, and buffers under multiple power domains. The accuracy of PSIJ methodology of the overall system is verified against the combined results of multiple circuit blocks when analyzed separately.
Empirical PSIJ simulation methodologies are examined with transistor-level SPICE simulations. By applying single-tone noise sources in circuit simulations, frequency-dependent jitter responses are compared with equation-based jitter transfer functions of a complete system.