Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Solving Power Integrity Test Challenges
Steve Sandler (Founder and CEO, Picotest)
Location: Room 203
Date: Wednesday, January 29
Time: 3:45pm - 4:25pm
Track: Sponsored Session
Vault Recording: TBD
Power Distribution Networks (PDNs) must provide many low-noise DC
power rails for sensitive loads such as microprocessors, DSPs, FPGAs and
ASICs. Higher current, lower voltage power rails impose tighter voltage
noise requirements. The need for greater efficiency requires many more
voltage rails. All of these demands along with higher channel frequencies
and edge rates put pressure on the design from SI, PI and EMI
perspectives.Power integrity measurements validate that the voltage power rail noise
voltage meets the specifications and assures that the noise doesn't
degrade signal integrity.
By attending this session, you will learn about the major noise sources in a
mixed signal application and how to:
• Accurately measure (2-port/3-port) impedance of a power distribution
network (PDN) and its sub-systems using a scope
• Analyze high frequency complex ripple in the presence of low tolerance
DC Power rails
• Automate time sequencing testing for multiple rails simultaneously
• Use your scope for many other critical tasks such as TIE Jitter, Frequency
Response, and TDR
• Perform various VNA functions in your scope