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DesignCon 2019 Presentation Viewer

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Spec-driven CTLE Model Synthesis Through Reinforcement Learning

Zao Liu (Staff Design Engineer, Xilinx)

Zhaoyin Daniel Wu (Principal Engineer, Xilinx Inc)

Location: Ballroom C

Date: Wednesday, January 30

Time: 2:50pm - 3:30pm

Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 08. Optimizing High-Speed Serial Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

To enable link level simulation for given CTLE specs, it is necessary to develop models to represent the behavior of these CTLE circuits under these specs. Traditionally, a lot of manual tuning and reiteration is needed to find the desirable pole/zero locations to build a CTLE transfer function to meet the spec. In this paper, given a set of frequency domain specs of CTLE, a reinforcement learning technique is used to automatically adjust the pole/zero location of the CTLE transfer function to meet the spec, which significantly reduced the manual work of finding the desired CTLE model.

Takeaway

CTLE modeling can be automated by Q-learning given the targeted specifications. (peaking, Nyquist, bandwidth, etc.)