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Statistical Signal Integrity Analysis of High-Bandwidth Memory (HBM) Interposer Channel Considering Non-linear Power/Ground Noise & SSO Noise

Youngwoo Kim (Post-doctoral Researcher, KAIST, Terabyte Interconnection and Package Lab.)

Location: Ballroom G

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

To achieve TB/s bandwidth, maintaining signal integrity in high-speed channel is mandatory. In the high-speed channel, not only channel parameters but also non-linear power/ground noise generated by SSO noise affect signal integrity. However, conventional simulators and eye-diagram estimation methods fail to accurately estimate the eye-diagram considering these noises. In this study, we propose fast and accurate statistical method which considers non-linear power/ground noise and SSO noise. The proposed method is applied for signal integrity analysis in HBM interposer channel. Proposed method estimates impacts of power/ground and SSO noise on HBM channel. Based on proposed method, hierarchical PDN design is optimized.

Takeaway

In this study, we propose statistical method which considers non-linear power/ground noise and SSO noise. The proposed method is applied for signal integrity analysis in HBM interposer channel. Proposed method estimates impacts of power/ground and SSO noise on HBM channel. Based on proposed method, hierarchical PDN design is optimized.

Intended Audience

High-bandwidth memory (HBM), Signal/Power Integrity basics, statistical analysis, hierarchical PDN, power/ground noise, simultaneous switching output (SSO) noise

Presentation Files

SLIDES_01_StatisticalSignalIntegrityAnalysisOf_Kim.pdf
PAPER_01_StatisticalSignalIntegrityAnalysisofHigh_Kim.pdf