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Statistical Signal/Power Integrity Analysis of High-Bandwidth Memory (HBM) Interposer Channel Considering SSO Noise, DVI & Burst Noise

Youngwoo Kim (Assistant Professor, NAIST)

Location: Ballroom D

Date: Thursday, January 30

Time: 9:00am - 9:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Due to reduced noise margin associated with increasing data rate, maintaining signal/power integrity is crucial. In high-speed channels, not only channel parameters but also non-linear power/ground noise associated with SSO, DVI and burst affect signal integrity. However, conventional simulators and eye-diagram estimation methods lose accuracy when these impacts are considered. In this paper, we propose statistical signal/power integrity analysis method considering power/ground noise associated with SSO, DVI-coding and burst mode. Especially burst noise generated by long bit pattern affected by the anti-resonance of the PDN is considered. The proposed method is applied for signal/power integrity analysis in HBM interposer channel.

Takeaway

In this paper, we propose statistical signal/power integrity analysis method considering power/ground noise associated with SSO, DVI-coding and burst mode. The proposed method is validated and compared with IBIS model. The proposed method is applied for signal integrity analysis in HBM interposer channel and optimal PDN design considering burst.

Intended Audience

For all audience