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Yuchun Lu (Principle Engineer, Huawei Technologies)
Zhilei Huang (Principle Engineer, Huawei Technologies)
Location: Ballroom A
Date: Thursday, January 30
Time: 2:50pm - 3:30pm
Track: 07. Optimizing High-Speed Serial Design, 09. High-Speed Signal Processing, Equalization & Coding
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Advanced DSP and FEC algorithms are explored. The advanced DSP schemes include the PR/(1+D) DFE, EoBD, MLSE. The joint analysis of DSP and FEC will be provided to show the performance enhancement due to the advanced DSP schemes. PR/(1+D) DFE, EoBD, MLSE may provide 1dB, 3dB, 4.5dB insertion loss extension under 2mVrms ICN. RS(576, 514) FEC may provide ~1.4dB insertion loss extension under 2mVrms ICN with (1+αD) DFE receiver; however if MLSE is applied, the improvement due to the higher overhead FEC is minor.
Advanced DSP and FEC provide performance enhancement for 112G PAM4 links. The advanced DSP algorithms, e.g. EoBD and MLSE will be explored. The joint analysis of DSP and FEC will be discussed.
Advanced DSP and FEC provide performance enhancement for 112G PAM4 links. The advanced DSP algorithms, e.g. EoBD and MLSE will be explored. The joint analysis of DSP and FEC will be discussed.