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The Hidden Challenges in 112-Gb Channel Design & Modeling

Alex Manukovsky  (Technical Lead, SI/PI Team, Intel)

Roee Bloch  (Senior Staff Hardware Engineering Lead, Marvell Semiconductor)

Shai Sayfan-Altman  (Senior Application Engineer, ANSYS)

Location: Ballroom D

Date: Wednesday, January 29

Time: 8:00am - 8:45am

Track: 13. Modeling & Analysis of Interconnects, 06. System Co-Design: Modeling, Simulation & Measurement Validation

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

A major aspect to consider in 112 Gb channel design is the effect of PCB manufacturing variation on channel properties. Since 112 Gb signals have a significant spectral content up to 56 GHz and a noticeable spectral content up to 75-80 GHz, it is important to maintain acceptable channel characteristics at these frequencies to ensure proper operation. Unfortunately, controlling channel properties becomes more complex as frequencies increase and small changes in geometry or material properties have a bigger impact on channel performance. Unlike in previous generations, design robustness plays a key role in successful 112 Gb channel design; some design works well on paper but fails once manufactured. Here we introduce some of the manufacturing aspects to consider while designing a 112 Gb channel and demonstrate the impact on channel performance by analyzing post manufacturing data gathered from the various fabrications of a case study 112 Gb system.


The lecture participant will learn the common pitfalls in the BKM's used today across the industry in design and modeling of high speed channels, will be given an introduction to robust channel design practices, and will be provided with the tools to meet the 112 Gb channel challenges.

Intended Audience

Basic S parameters knowledge,
Basic understanding of PCB Package design,
Basic understanding of COM and ERL metrics,
Basic knowledge in SI simulation.

Presentation Files