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The Problem of Comparator Metastability in High-speed Wireline Receivers

Sina Naderi Shahi (Senior Designer, Huawei Technologies Canada)

MarcAndre LaCroix (Distinguished Engineer, Huawei Technologies Canada)

Semyon Lebedev (Principle Engineer, Huawei Technologies Canada)

Davide Tonietto (Director of SerDes Development, Huawei Canada)

Location: Ballroom C

Date: Thursday, January 31

Time: 9:00am - 9:45am

Track: 08. Optimizing High-Speed Serial Design, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

With evolving ADC-based high speed transceivers, ADC comparator metastability induced error (MIE) and its impact on system performance have to be addressed. These information allows an efficient ADC design for optimized power and area.
In order to investigate the impact of MIE on total system performance, knowledge of the MIE probability for each bit is essential. A simplified analytical approach is developed for calculation of MIE for each bit. We then study the MEI impact on system BER. Finally, the concept is verified using time-domain simulation and ultimately validated by measurements.


Knowledge of metastability induced error (MIE) probability and its impact on system performance allow efficient ADC design. This information helps finding the limit for acceptable MIE probability and possibly relax ADC parameters in order to save power and area.

Intended Audience

Hands-on knowledge of ADC and SerDes.

Presentation Files