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The SI/PI Modeling & Measurement of Memory System by Probing on Top of DRAM Package

WonSuk Choi (SI/PI Engineer, Samsung Electronics)

SangKeun Kwak (Principal Engineer, Samsung Electronics)

Location: Ballroom E

Date: Wednesday, January 29

Time: 11:00am - 11:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Continuous increase in the performance and speed of computer systems has led to more frequent field failures of memory systems. As a result, accurate measurement and modeling are becoming of utmost importance for memory vendors in order to guarantee the electrical reliability of their products. However, conventional on-chip measurement methodologies such as probing on the decoupling capacitor or a use of a test interposer between chip pads and measurement points. In this paper, we propose a novel method of measuring Signal Integrity and Power Integrity (SI/PI) performances of DRAM operation by directly probing on top of DRAM package. With this proposed test package, we prove the effectiveness of monitoring on-chip operation through simulation and measurement and hence, effectively enhance the level of SI/PI modeling and predictability of memory systems.

Takeaway

A new method of measuring SI/PI of memory system is presented based on directly probing on top of DRAM package. The effectiveness of this proposal for estimating DRAM operation in chip pad is verified through comparison between simulation and measurement.

Presentation Files

Slides_DesignCon2020_Track01_ProbingOnTopOofDRAM_Choi1.pdf
DesignCon_2020_Track01_ProbingOnTopOfDRAM_Choi.pdf