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The SI/PI Modeling & Measurement of Memory System by Probing on Top of DRAM Package

WonSuk Choi (Staff Engineer, Samsung Electronics)

SangKeun Kwak (Principal Engineer, Samsung Electronics)

Location: Ballroom E

Date: Wednesday, January 29

Time: 11:00am - 11:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Continuously increasing computer systems' speed has led to more frequent field failures of memory system than the past. Therefore, accurate measurement and modeling correlation is getting important for memory vendors to guarantee the electrical reliability of their products.
In this paper, we propose a novel method of measuring Signal Integrity and Power Integrity (SI/PI) performances of DRAM operation by directly probing on top of DRAM package instead of using a conventional test interposer. With this proposed test package, we improve the correlation between simulation and measurement and hence, effectively enhance the level of SI/PI modeling and predictability of memory system.


A new method of measuring SI/PI of memory system is presented based on directly probing on top of DRAM package. The effectiveness of this proposal for estimating DRAM operation in chip pad is verified through correlation between simulation and measurement.