April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Speaker:
Keeyoung Son (ph.D candidate, Korea Advanced Institute of Science and Technology)
Authors:
Keunwoo Kim (ph.D candidate, Korea Advanced Institute of Science and Technology)
Minsu Kim (MS Candidate, Korea Advanced Institute of Science and Technology)
Taein Shin (ph.D candidate, Korea Advanced Institute of Science and Technology)
Hyunwook Park (ph.D candidate, Korea Advanced Institute of Science and Technology)
Seongguk Kim (ph.D candidate, Korea Advanced Institute of Science and Technology)
Joungho Kim (Professor, Korea Advanced Institute of Science and Technology)
Seonguk Choi (Graduate Student (PhD), Korea Advanced Institute of Science and Technology, KAIST)
Joonsang Park (Ph.D. Candidate, Korea Advanced Institute of Science and Technology)
Jihun Kim (Graduate student (M.S), Korea Advanced Institute of Science and Technology, KAIST)
Haeyoen Rachel Kim (Master Candidate, KAIST)
Location: Ballroom F
Date: Thursday, April 7
Time: 11:15 am - 12:00 pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Theme : Consumer Electronics
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
Thermal issues affect to signal integrity(SI) performances. Therefore, thermal management systems are essential. One of high-end thermal management systems is embedded cooling structure(ECS). However, ECS has difficulties of adopting to 2.5D-ICs. Because ECS needs sufficient thickness for structural reliability.
Because of thickness limitation, 2.5D-ICs module need to install ECS inside the interposer or PCB, which located under the chip. Hence, 2.5D-ICs cooled by ECS indirectly. Indirect cooling from ECS has low vertical cooling efficiency due to underfill. It caused heat accumulation on 2.5D-ICs which degrades SI performances.
Therefore, we proposed novel thermal transmission line(TTL) to support ECS for lowering temperature and smoothing thermal gradients of 2.5D-ICs. TTL is new interconnection which focused on heat transfer. TTL is installed across the on-chip TSV array and connected to fluidic-TSV of ECS to transfer heat to coolant, directly. Due to TTL, it can overcome thermal management limitation due to underfill.
For verification, we designed and analyzed HBM in terms of thermal integrity(TI) and SI. For TI analysis, we analyzed temperature distribution and thermal resistance. For SI analysis, we analyzed HBM channel and 3D CDN considering operating temperature distribution with and without TTL. The results showed the proposed TTL improved temperature uniformity and 3D CDN skew dramatically.
This paper tackles limitations of embedded cooling structure, requiring sufficient die thickness and low cooling efficiency for 2.5D ICs. Proposed thermal transmission line transfer heat inside stacked dies to coolant for lowering temperature and smoothing thermal gradients. Therefore, it improves SI performances of off-chip interconnections and 3D global interconnections, dramatically.