DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Timing Assistant for Dynamic Voltage Drop Impact on Maximum Timing Pushout

Norman Chang (Chief Technologist, ANSYS)

Hao Zhuang (Software Engineer, Google)

Wentze Chuang (Graduate Student in Computer Science, National Taiwan University)

Ganesh Tsavatapalli (Sr. Software Engineer, ANSYS)

Sankar Ramachandran (Technical Product Manager, ANSYS)

Rahul Rajan (Sr. Application Engineer, ANSYS)

Joao Jeada (Chief Technologist, ANSYS)

Ying-Shiun Li (Director, ANSYS)

Yaowei Jia (director, ANSYS)

Mathew Kaipanatu (Sr. Software Engineer, ANSYS)

Suresh Kumar Mantena (Sr. Software Engineer, ANSYS)

Ming-Chih Shih (Sr. manager, ANSYS)

Roger Jang (Professor, National Taiwan University)

Location: Ballroom E

Date: Wednesday, January 30

Time: 8:00am - 8:45am

Track: 15. Machine Learning for Microelectronics, Signaling & System Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Introductory

Large integrated circuits, such as System-on-a-Chip (SoC) designs, often suffer from a reduced operational frequency due to various timing constraints. This reduction in operating frequency is often caused by the impact of dynamic voltage drop on setup timing violations, often referred to as maximum timing push-off. This problem is exacerbated in advanced FinFET designs such as 7nm/5nm due to smaller VDD, insufficient switching scenario coverage, and larger local power density. This paper proposes an novel method using machine learning technique to enable critical scenario(s) predictor for running dynamic voltage drop analysis and critical timing path(s) predictor for accurate timing analysis.


setup timing constraints, setup timing violation, maximum timing push-off, dynamic voltage drop, 7nm/5nm FinFET designs, machine learning, deep learning, deep neural network, Static Timing Analysis (STA)

Intended Audience

No prerequisites

Presentation Files