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Timing Assistant for Dynamic Voltage Drop Impact on Maximum Timing Pushout

Norman Chang (Chief Technologist, ANSYS)

Hao Zhuang (Software Engineer, Google)

Wentze Chuang (Graduate Student in Computer Science, National Taiwan University)

Ganesh Tsavatapalli (Sr. Software Engineer, ANSYS)

Sankar Ramachandran (Technical Product Manager, ANSYS)

Rahul Rajan (Sr. Application Engineer, ANSYS)

Joao Jeada (Chief Technologist, ANSYS)

Ying-Shiun Li (Director, ANSYS)

Yaowei Jia (director, ANSYS)

Mathew Kaipanatu (Sr. Software Engineer, ANSYS)

Suresh Kumar Mantena (Sr. Software Engineer, ANSYS)

Ming-Chih Shih (Sr. manager, ANSYS)

Roger Jang (Professor, National Taiwan University)

Location: Ballroom E

Date: Wednesday, January 30

Time: 8:00am - 8:45am

Track: 15. Machine Learning for Microelectronics, Signaling & System Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Introductory

Large integrated circuits, such as System-on-a-Chip (SoC) designs, often suffer from a reduced operational frequency due to various timing constraints. This reduction in operating frequency is often caused by the impact of dynamic voltage drop on setup timing violations, often referred to as maximum timing push-off. This problem is exacerbated in advanced FinFET designs such as 7nm/5nm due to smaller VDD, insufficient switching scenario coverage, and larger local power density. This paper proposes an novel method using machine learning technique to enable critical scenario(s) predictor for running dynamic voltage drop analysis and critical timing path(s) predictor for accurate timing analysis.

Takeaway

setup timing constraints, setup timing violation, maximum timing push-off, dynamic voltage drop, 7nm/5nm FinFET designs, machine learning, deep learning, deep neural network, Static Timing Analysis (STA)

Intended Audience

No prerequisites

Presentation Files

SLIDES_15_TimingAssistantforDynamicVoltage_Chang.pdf
PAPER_15_TimingAssistantforDynamicVoltage_Chang.pdf