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Top-Down Jitter Specification Approach for HBM System Optimization

Nanju Na (Hardware Design Engineer, Xilinx)

Thomas To (Technical Director, Xilinx)

Anna Wong (Senior Manager, Xilinx)

Location: Ballroom B

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

This paper presents a top-down design approach for HBM system on interposer based on jitter transfer characteristics in component blocks from different suppliers in configuration. Jitter transfer functions are formulated in blocks with different jitter aspects in components to meet overall target performance in system integration. Jitter factors in Phy IO&buffer and interposer interconnects are different with interposer response to EM as major jitter factor such as crosstalk or waveform distortion while on-die timing uncertainties are factors of silicon circuits. HBM system design is analyzed with those jitter specifications and correlated with measured jitter data collected in hardware V&C.


HBM system involves multiple parties to meet performance. This paper develops a definition methodology to capture the critical performance requirement. This enables HBM system to perform to the targeted specification.

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