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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Marianne Nourzad (Analog Engineer, Intel)
Hsinho Wu (Design Engineer, Intel)
Jong-Ru Guo (Analog Engineer, Intel)
Zuoguo (Joe) Wu (Senior Principal Engineer, Intel)
Masachi Shimanouchi (Design Engineer, Intel)
Mohiuddin Mazumder (Senior Principal Engineer, Intel)
Mike Li (Fellow, Intel)
John Yang (Analog Engineer, Intel)
Location: Ballroom G
Date: Thursday, April 7
Time: 11:15 am - 12:00 pm
Track: 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER, 12. Applying Test & Measurement Methodology
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
The jitter characterization and measurement methodology for NRZ high speed I/O systems are well established in the industry. While PAM-4 signal jitter measurement procedures are already defined in IEEE 802.3 and OIF-CEI, accurate and reliable jitter assessments remain challenging as the data rates increase to 100Gbps+ in serial links. Concurrently, with the PCIe 6.0 moving to PAM-4 encoding, and this standard having its specific measurement constraints, the development of new methodologies to accurately assess the jitter impact on the link performance is required. This paper reviews and explains existing jitter measurement procedures currently used in the industry, while presenting the new methodology developed for the PCIe 6.0 standard as well as factors such as noise and ISI to consider while attempting such measurements in laboratory settings.
The audience will gain the knowledge on PAM-4 jitter measurement techniques, its challenges and limitations for high-speed serial links; as well as specific measurement methodologies for PCIe 6.0 and Ethernet standards.
For audience with knowledge on high-speed serial links, jitter and noise components, and equalization schemes in serial communication links