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Tutorial – Advanced IBIS-AMI Techniques for 32 GT/s & Beyond

Greg Edlund (Senior Engineer, IBM)

Kumar Keshavan (Software Architect, Cadence Design Systems, Inc.)

Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems, Inc.)

Ambrish Varma (Senior Principal Software Engineer, Cadence Design Systems)

Ken Willis (Product Engineering Architect, Cadence Design Systems)

Location: Ballroom A

Date: Tuesday, January 29

Time: 9:00am - 11:50am

Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors

Session Type: Tutorial

Vault Recording: TBD

Audience Level: Advanced

IBIS-AMI is a cornerstone for designing serial interfaces like PCI Express Gen 5, which are sensitive to mistakes on the order of 2 ps. Our tutorial will cover advanced topics that deepen the user's understanding of modeling to this level of accuracy. How does clock data recovery work in PAM4 with three separate eyes? Do the simulator and the hardware use the same technique to search for optimum equalizer settings? How do the TX and RX interact during back-channel optimization? What are the differences between TX and RX random jitter?


Attendees of this tutorial can expect to gain a deeper understanding of the functional behavior of SerDes adaptive equalization and clock data recovery circuits, how the model represents these circuits, and how the simulator treats the model parameters.

Intended Audience

Experience using IBIS-AMI models and simulating SerDes interfaces. Exposure to equalization techniques. Familiarity with jitter decomposition.

Presentation File