April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Tutorial – Design & Verification for High-Speed I/Os at 10 to 112 & 224Gbps with Jitter, Signal Integrity & Power Optimized
Speaker:
Mike Li (Fellow, Intel)
Location: Ballroom EF
Date: Tuesday, April 5
Time: 9:00 am - 11:30 am
Track: 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER
Format: Tutorial
Theme : High-speed Communications
Education Level: All
Pass Type: All Access Pass
Vault Recording: TBD
Audience Level: All
This tutorial reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (28, 20, 14, 10, 7, 5 nm) technology advancements for high-speed links, with an emphasis on jitter, noise, signal integrity, and FEC for 10 -106 and 224 Gbps high-speed I/Os (e.g., GbE (10G, 40G, 100G, 200G, 400G, 800G, 1.6 T), CEI/OIF (11G, 18-28G, 36-58G, 72-116G, and 144-232G), Fibre Channel (16G, 32G, 64G, 128G+), and PCI Express (8G, 16G, 32G, 64G+). Example studies on design and validation methods will be presented.
Takeaway
Basics knowledge on high-speed link architectures, jitter, noise, SNDR, RL/ERL, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps and 224 Gbps link design and verification with jitter, noise, SNDR, signal integrity, FEC/performance, and power optimization.
Intended Audience
Anyone who likes to learn the basics on the jitter, noise, highs-speed I/Os, as well as the latest technologies and developments in those areas.
