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Tutorial – Design & Verification for High-Speed I/Os at 10- to 112-Gbps with Jitter, Signal Integrity & Power Optimization

Mike Li  (Fellow, Intel)

Location: Ballroom C

Date: Tuesday, January 28

Time: 9:00am - 11:50am

Track: 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC)

Format: Tutorial

Pass Type: All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Basics knowledge on high-speed link architectures, jitter, noise, SNDR, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps link design and verification with jitter, noise, SNDR, signal integrity, FEC/performance, and power optimization.


This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (28, 20, 14, 10, 7nm) technology advancements for high-speed links, with an emphasis on jitter, noise, signal integrity, and FEC for 10 -112 Gbps high-speed I/Os (e.g., GbE (10G, 40G, 100G, 200G, 400G), CEI/OIF (11G, 20-28G, 40-60G, 80-120G), Fibre Channel (16G, 32G, 64G, 128G), and PCI Express (8G, 16G, 32G, 64G). Example studies on design and validation methods will be presented.

Intended Audience

This tutorial is designed for two types of audience. The first is young, recently graduated engineers and engineers just getting into the communication, jitter, and high-speed fields. Those audiences like to learn the basics, as well as the latest information in a condensed course. The other audiences are experienced and returning engineers who are interested in the latest information, but still like the basics be reviewed and refreshed. Accordingly, this tutorial covers basic, cumulative, and continuing topics, as well as the latest evolving and emerging new topics, to meet the different needs and expectations of the diverse audiences.