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DesignCon 2019 Presentation Viewer

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Tutorial – Design & Verification for High-Speed I/Os at 10 to 112Gbps With Jitter, Signal Integrity & Power Optimization

Mike Li (Fellow, Intel)

Location: Ballroom D

Date: Tuesday, January 29

Time: 1:30pm - 4:30pm

Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors

Session Type: Tutorial

Vault Recording: TBD

Audience Level: All

This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (28, 20, 14, 10 nm) technology advancements for high-speed links, with an emphasis on jitter, noise, signal integrity, and FEC for 10 -112 Gbps high-speed I/Os (e.g., GbE (10G, 40G, 100G, 200G, 400G), CEI/OIF (11G, 20-28G, 40-60G, 80-120G), Fibre Channel (16G, 32G, 64G, 128G), and PCI Express (8G, 16G, 32G). Example studies on design and validation methods will be presented.

Takeaway

Basics knowledge on high-speed link architectures, jitter, noise, SNDR, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps link design and verification with jitter, noise, SNDR, signal integrity, FEC/performance, and power optimization.

Intended Audience

Conceptual knowledge on the jitter, noise, and integrity, and high-speed I/O.