DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!


DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Tutorial – Design With Confidence Using 16Gb/s GDDR6 Memory

Tim Hollis (Distinguished Member of the Technical Staff – Signal Integrity R&D Lead, Micron)

Michael Richter (Principal Engineer, Micron)

Christopher Kuhn (Engineer, Micron)

Shu Wang (Lead Software Engineer, Cadence)

Marc Greenberg (Product Marketing Group Director, Cadence)

Location: Ballroom B

Date: Tuesday, January 29

Time: 1:30pm - 4:30pm

Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques

Session Type: Tutorial

Vault Recording: TBD

Audience Level: Intermediate

Though standard DRAM speeds have continued to increase, focus has been primarily on density — often at the expense of bandwidth. GDDR has taken a different path, focusing on high bandwidth. With GDDR6 speeds reaching 14 Gb/s and beyond, it is critical to have designs that are well planned, simulated and implemented. This session will provide best practices and techniques of how modern high bandwidth memory system designs should care for single-ended signal and power integrity, as well as utilize GDDR6 DRAM features that help reliably achieve these high data rates.

Takeaway

GDDR6 is a viable off-the-shelf higher memory bandwidth solution
The tools and techniques for designing a 16Gbps single-ended I/O memory are readily available

Intended Audience

Basic understanding of PCB design and memory architectures

Presentation File

SLIDES_07_DesignWithConfidenceUsing16Gbps_Hollis.pdf