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Tutorial – Design With Confidence Using 16Gb/s GDDR6 Memory

Tim Hollis (Distinguished Member of the Technical Staff – Signal Integrity R&D Lead, Micron)

Michael Richter (Principal Engineer, Micron)

Christopher Kuhn (Engineer, Micron)

Shu Wang (Lead Software Engineer, Cadence)

Marc Greenberg (Product Marketing Group Director, Cadence)

Location: Ballroom B

Date: Tuesday, January 29

Time: 1:30pm - 4:30pm

Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques

Session Type: Tutorial

Vault Recording: TBD

Audience Level: Intermediate

Though standard DRAM speeds have continued to increase, focus has been primarily on density — often at the expense of bandwidth. GDDR has taken a different path, focusing on high bandwidth. With GDDR6 speeds reaching 14 Gb/s and beyond, it is critical to have designs that are well planned, simulated and implemented. This session will provide best practices and techniques of how modern high bandwidth memory system designs should care for single-ended signal and power integrity, as well as utilize GDDR6 DRAM features that help reliably achieve these high data rates.


GDDR6 is a viable off-the-shelf higher memory bandwidth solution
The tools and techniques for designing a 16Gbps single-ended I/O memory are readily available

Intended Audience

Basic understanding of PCB design and memory architectures

Presentation File