April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Tutorial – PAM6 Signaling: A Potential Candidate at 224Gbps


Geoff Zhang  (Distinguished Engineer, AMD)

Zhaoyin Daniel Wu  (Principal Engineer, AMD)

Jinbiao Xu  (Senior Staff Engineer, AMD)

Hongtao Zhang  (Principal Engineer, AMD)

Location: Ballroom AB

Date: Tuesday, April 5

Time: 9:00 am - 11:30 am

Track: 09. High-Speed Signal Processing, Equalization & Coding/FEC, 07. Optimizing High-Speed Link Design

Format: Tutorial

Theme : Data Centers

Education Level: All

Pass Type: All Access Pass

Vault Recording: TBD

Audience Level: All

112Gbps serial interface has been in the development phase using PAM4 signaling. The next speed node is 224Gbps. Due to the excessive bandwidth demanding from PAM4, the industry is considering other signaling candidates for 224Gbps for trade-off of power and performance and backward-compatibility. This tutorial provides an in-depth background of PAM6 signaling with several different flavors of implementations to benefit the industry. PAM6 extends the signal coding from 1-D to 2-D, thus it is fundamentally different from PAM4 and NRZ. PAM6 is also conceptually different from QAM. Illustrative examples are provided to make this tutorial a pleasant hands-on learning experience.


After attending this tutorial, the attendees shall understand the uniqueness of PAM6, different flavors within the PAM6 family and their pros and cons in terms of performance and implementation complexity. PAM6 is fundamentally different from PAM4 and NRZ. The concept of SNR vs bandwidth is also emphasized throughout the tutorial.

Intended Audience

Basic idea of high-speed serial link analysis Basic concept of signal modulation, channel bandwidth and system SNR