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Updates on the Challenges of Characterizing 112 Gbps/Lane Designs

Rob Sleigh  (Strategic Product Planner, Keysight Technologies)

John Calvin  (Senior Strategic Planner, IP Wireline Solutions, Keysight Technologies)

Location: Great America 1

Date: Thursday, January 30

Time: 9:20am - 10:05am

Track: Keysight Education Forum

Vault Recording: TBD

Test instrumentation is an integral part of the move to 112 Gbps/lane designs. The proposed reference receivers being investigated for these high speed SERDES are making a tradeoff between the performance gains of high tap count DFE’s compared to less complex FFE based equalization methods. While these committees have not converged on a definitive equalization strategy yet, the T&M contributions are supporting the combinations of FFE’s, CTLE’s and DFE. In most cases these filters operate orthogonally enough where they can be optimized sequentially to specific optimization targets such as eye height, DDJ minimization or pulse response optimization. This presentation will review efforts in test tools that are closely tracking standards work and describe optimization methods ensuring test instrumentation tracks the reference receivers with high accuracy and repeatability across different classes to tools.