April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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USB Type-C® Standard PHY testing


Mike Engbretson  (Product Manager – High Speed Oscilloscope Solutions, Teledyne LeCroy)

Location: Mission City Ballroom B5

Date: Wednesday, April 6

Time: 11:15 am - 12:00 pm

Track: Sponsored Session

Format: Sponsored Session

Education Level: All

Pass Type: 2-Day Pass, All Access Pass, Expo Pass

Vault Recording: TBD

Audience Level: All

Over the last few years, USB and DisplayPort have adopted Intel’s Thunderbolt PHY specification as a ‘building block’ for USB4™ and DisplayPort™ specifications at the physical layer. The highest data rates over the USB-C® are now 20Gb/s on each lane for data throughput of 40Gb/s on two lanes for USB4 and 80Gb/s over four lanes for DisplayPort 2.0. This session will discuss the latest PHY Transmitter (Source) and Receiver (Sink) test methods for USB4 and DisplayPort 2.x as well as touch on the latest PHY logical layer (PHY-Logic) debug tools for USB Type-C system integration.