April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Validation of Achieving 200Gbps Signaling per Electrical Lane Over 1 Meter of Passive Twinaxial Copper Cable


Christopher DiMinico  (President/CTO, MC Communications/PHY-SI LLC/SenTekse)

Michael Klempa  (Electrical Engineer, Amphenol ICC)

David Nozadze  (Signal Integrity Technical Leader, Cisco Systems)

Michael Rowlands  ( SI Engineering Manager, Amphenol HSC)


Mike Resso  (Signal Integrity Application Scientist, Keysight Technologies)

Curtis Donahue  (Global Technology Manager for High Speed Digital Interfaces, Rohde & Schwarz)

Oj Danzy  (Senior RF and Mcrowave Application Engineer, Keysight Technologies)

Richard Mellitz  (Distinguished Engineer at Samtec, Samtec)

Mike Sapozhnikov  (Principal Engineer/Signal Integrity Manager, Cisco Systems)

Amendra Koul  (Principal Engineer - Signal Integrity, Cisco Systems)

Adee Ran  (hardware principal engineer , Cisco Systems)

Upen Reddy Kareti  (Distinguished Engineer, Cisco Systems)

Location: Ballroom H

Date: Wednesday, April 6

Time: 8:00 am - 8:45 am

Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Format: Technical Session

Theme : High-speed Communications

Education Level: Introductory

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: Introductory

The paper will explore details of a process for validation of achieving 200 Gb/s signaling per electrical lane over 1 meter of passive twinaxial copper cable assemblies utilizing predictive simulation models and measurements. Predictive simulation models include the channel operating margin (COM) and associated parameters as well as s-parameter models for cable assemblies, test fixtures, and channels. Considerations for single-ended and mixed-mode s-parameter characterization of channel asymmetry and reciprocity will be explored. Identification of signal rise time to be used in predictive models as well as mated test fixture parameters such as integrated crosstalk noise (ICN) and insertion loss deviation (ILD) will be addressed. The transmission parameters and measurements of test fixtures are explored as well as their usage in testing at the various channel test points. The channel insertion loss budget between the transmitter and the receiver consisting of the host printed circuit board, the media dependent interface (MDI) and the copper media will be considered in detail including assumed BGA and VIA insertion losses and impact of measurement reference impedance. The PHYs mechanical/electrical interfaces medium dependent interfaces (MDIs) and types will be discussed as related to cable assembly and mated test fixture transmission and crosstalk characteristics and COM.


Understanding of validation of achieving 200 Gb/s signaling per electrical lane over 1 meter of passive twinaxial copper cable in support of developments in the IEEE 802.3df Task Group to create physical layer (PHY) specifications for operating speeds of 200 Gb/s, 400 Gb/s, 800 Gb/s, and 1.6 Tb/s based on 200 Gb/s signaling per electrical lane.