DesignCon 2022 Schedule Builder

The completion of SerDes design validation is typically gated by the availability of SystemVerilog analog behavioral models. As data rates increase beyond 100Gb/s, transistor technologies scale, and design margins shrink, achieving analog design targets and predicting analog design completion is becoming increasingly difficult. This, in turn, delays the availability of behavioral models and degrades design verification quality. We present a methodology to automatically generate SystemVerilog behavioral models from SerDes system models, which are available prior to analog design completion. This approach alleviates analog design dependencies, thus shifting left the design validation timeline. As the analog design evolves, the system models are refined with simulation data, and the SystemVerilog models are refreshed to maintain design correlation.

Takeaway

A system-model-centric method of generating port-matched analog behavioral models will be demonstrated. Configurable system models allow for the customization of analog behaviour and functionality based on use cases. As the system models evolve from abstract behaviour to analog-representative behaviour, the System Verilog models can be refreshed automatically.