April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Validation Shift-left: Enabling Early SerDes Mixed-signal Validation


David Halupka  (Founder & Director, SeriaLink Systems)

Aleksey Tyshchenko  (Founder, CEO & Director, SeriaLink Systems)

Richard Allred  (Senior Developer, MathWorks, Inc.)


Marc Erickson  (Principal SW Engineer, MathWorks, Inc.)

Tripp Worrell  (SI/AMS/SiSoft Development Manager, MathWorks, Inc.)

Barry Katz  (Director RF/EM/SI/AMS / President/CEO, MathWorks, Inc. / SiSoft)

Jesson John  (Industry Manager, Analog/Mixed-Signal Segment, MathWorks, Inc.)

Ranjan Sahoo  (Circuit and System Architect, NXP Semiconductors)

Lenin Patra  (VP/Marvell Fellow, Marvell Semiconductor)

Venu Balasubramonian  (Senior Director, Product Marketing, Marvell Semiconductor)

Pragati Tiwary  (Principal Software Engineer, MathWorks, Inc.)

Location: Ballroom G

Date: Wednesday, April 6

Time: 3:00 pm - 3:45 pm

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Optimizing High-Speed Link Design

Format: Technical Session

Theme : High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

The completion of SerDes design validation is typically gated by the availability of SystemVerilog analog behavioral models. As data rates increase beyond 100Gb/s, transistor technologies scale, and design margins shrink, achieving analog design targets and predicting analog design completion is becoming increasingly difficult. This, in turn, delays the availability of behavioral models and degrades design verification quality. We present a methodology to automatically generate SystemVerilog behavioral models from SerDes system models, which are available prior to analog design completion. This approach alleviates analog design dependencies, thus shifting left the design validation timeline. As the analog design evolves, the system models are refined with simulation data, and the SystemVerilog models are refreshed to maintain design correlation.


A system-model-centric method of generating port-matched analog behavioral models will be demonstrated. Configurable system models allow for the customization of analog behaviour and functionality based on use cases. As the system models evolve from abstract behaviour to analog-representative behaviour, the System Verilog models can be refreshed automatically.