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Jungil Son (Staff Engineer, Samsung Foundary)
Jun So Pak (Pricipal Engineer, Foundry Samsung Foundry)
Location: Ballroom E
Date: Thursday, January 30
Time: 11:00am - 11:45am
Track: 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
This proposal is to use Verilog-a models to perform the more realistic system-level PDN analysis than general analysis method. One of the models is the VRM model. The additional voltage drop due to limited current supply capability of VRM and the DC compensation due to feedback function of VRM can be considered using our model. The other model is the current source which can scale current scenario automatically dependent on voltage at bump, so pessimism of voltage drop using ideal current source can be removed.
This proposal is a methodology that utilizes verilog-a for system-level PI simulation. The verilog-a models (VRM with adjustable current supply capability, Current source with automatic scalability dependent on the voltage noise at bump) can be used to analyze the more realistic system-level voltage drop performance.
This proposal is a methodology that utilizes verilog-a for system-level PI simulation. The verilog-a models (VRM with adjustable current supply capability, Current source with automatic scalability dependent on the voltage noise at bump) can be used to analyze the more realistic system-level voltage drop performance.