This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.
DesignCon 2020 Schedule Builder
Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
What You Need to Know Before Simulating DDR5 Memory Designs
Hee-Soo Lee (SerDes/DDR Product Owner, Keysight Technologies)
Location: Great America 1
Date: Thursday, January 30
Time: 11:05am - 11:45am
Track:
Keysight Education Forum
Vault Recording: TBD
It has taken multiple years to shape DDR5 memory definitions and specifications by the industry. Some semiconductor manufacturers have already started powering on and validating DDR5 memory although the final specification is not yet complete. DDR5 memory shares many similar features to its predecessor, DDR4; but also some features that are very different, such as equalization on the DRAM receiver. Without simulating proper channel equalization, it is almost impossible to open the eye at higher speed such as 6400Mbps, and predict what the design margin will be. In this paper, you will learn the details of DDR5 memory design, which models and simulation technologies are needed for an accurate simulation, and how design/simulation challenges are addressed with Memory Designer in PathWave ADS.