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Wideband Jitter Tracking for Low Power Clock Forwarded I/O Links

Armin Tajalli (Analog Architect, Kandou Bus)

Location: Ballroom E

Date: Thursday, January 31

Time: 8:00am - 8:45am

Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Advanced clocking schemes are introduced to improve link performance in forwarded clock serial I/O transceivers. To maximize jitter tracking characteristics of receiver, and increase horizontal eye opening and save power, new techniques to design very high bandwidth phase-locked loop circuits will be presented. Practical examples are presented to show effectiveness of the proposed clocking scheme.

Takeaway

(1) proper clocking system design helps to considerably reduce energy consumption in short-reach links; (2) high bandwidth jitter tracking helps to relax design constraints on serial data transmitter, hence reduce the design time and result into a more robust system; and (3) novel advanced techniques to extend bandwidth of PLLs.

Intended Audience

The audience are expected to have basic knowledge on the following topics: clocking, phase locked loops, and clock forwarded transceiver architecture.

Presentation Files

SLIDES_08_WidebandJitterTrackingforLow_Tajalli.pdf
PAPER_08_WidebandJitterTrackingforLow_Tajalli.pdf