DesignCon 2022 Schedule Builder

Pervez M. Aziz received his B.S., M.S., Ph.D. degrees from the University of Pennsylvania in 1990, 1991, and 1996 respectively. After working on delta-sigma A/D converter architectures for his doctoral thesis, he joined AT&T Microelectronics Group / Bell Laboratories in 1995 to work on architecture development for magnetic recording read channels. This group subsequently became part of Lucent Technologies, then Agere Systems, and LSI Corp in 2007. LSI Corp. was acquired by Avago Technologies in May, 2014. Dr. Aziz was a Distinguished Engineer at Avago. From 1995 to 2003 while contributing to several generations of commercially designed read channels, he worked on various aspects of architecture development and analysis including equalization, timing recovery, servo signal processing, construction and implementation of modulation and distance enhancing codes, as well as Viterbi and postprocessor based detection. In 2003 he joined the Serdes architecture group where he worked on adaptive equalization and clock / data recovery architecture / algorithm development and analysis for commercially designed high speed multi-gigabit Serdes channels. In Oct 2014, Dr. Aziz joined Nvidia Corporation where he is a Senior Principal Engineer. He has worked on serial link architecture development, statistical/transient tool development, and performance analysis for both NRZ and multi-level modulation, equalization, detection, and clock data/recovery. He has also developed transient and analytic models for forward error correction. Dr. Aziz's interests also include bit cycle accurate modeling and functional verification of digital signal processing circuits and modeling of analog circuits. He has published 6 book chapters, 11 journal papers, 24 conference papers and numerous internal technical documents and architecture specifications. He is a recipient of the Electronics Letters Premium Award. He holds about 50 U.S. patents. Dr. Aziz is a member of Eta Kappa Nu, Tau Beta Pi and is a Senior Member of the IEEE. 

Presenting:

• Panel – What is Needed for 224Gbps? System & Chip Vendors Perspective