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DesignCon 2020 Schedule Builder
Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Roee Bloch is currently Senior Staff Hardware Engineering Lead at Marvell Semiconductor. In his former position as Technical Leader at Conformance Team for Intel, he was responsible for compliance testing at 56GB/s PAM-4, 100GB/s NRZ, PCIe Gens 1-4, researching for new technologies and new test equipment that will be suitable for next generation of future products. Doing also simulation using HFSS and other tools such as ADS, Simbeor High Speed simulators He has more than 5 years of experience in signal integrity, system simulation, system testing, PCB design and validation. He is also Instructor at Technion in Several courses such as: Logic Systems, Assembler 8086, computer structures, Quartus simulation and TTL Lab. He received his B.Sc. from the Holon Institute of Technology at 2009