April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.
Joseph Boon Hock, product development engineer, Intel
Joseph Kho Boon Hock is a validation technical lead at Intel Corporation and Altera corporation, focusing on electrical validation of HSIO. He leads electrical validation and product development for several generations of HSIO on FPGA products. This cover SEDER technology from 6Gbps generation to 112Gbps generation. He has 6 technical publications and 3 U.S patterns. He received his B.S in Electronic Engineering from Multimedia University, Malaysia.
Presenting:
