April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.
Marc Erickson, Principal SW Engineer, MathWorks, Inc.
Marc has spent his career in the design, verification, and tool development for large ASICs and FPGAs at Intel, Teradyne, and as a consultant. For the last 15 years he has been a technical lead at MathWorks making contributions for the HDL Verifier, SoC Blockset, SDR-Zynq, and Vision-Zynq products. BSEE from Princeton University.
Presenting:
