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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Marc has spent his career in the design, verification, and tool development for large ASICs and FPGAs at Intel, Teradyne, and as a consultant. For the last 15 years he has been a technical lead at MathWorks making contributions for the HDL Verifier, SoC Blockset, SDR-Zynq, and Vision-Zynq products. BSEE from Princeton University.