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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Yohan Frans received B.S. degree in electrical engineering from Bandung Institute of Technology, Indonesia in 1995 and M.S. degree in electrical engineering from Stanford University, California in 2001. From 2001 to 2012, he was with Rambus Inc. where he worked on high-performance and low-power serial links and memory interfaces as circuit design engineer, circuit architect, and design manager. Since 2012 he has been with Xilinx Inc, San Jose, CA. He is currently leading world-wide engineering teams as VP of Engineering at Xilinx Wired and Wireless Communication Business Unit, developing high-speed wireline transceivers for advanced FPGA. His current interests include high-speed mixed-signal circuit design, serial link architecture, transmitter/receiver design, PLL/DLL, memory interfaces, and low-power circuit architectures. He is a member of ISSCC Wireline Sub-committee.