April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.

Xu JiangSenior Signal Integrity EngineerLuxshare-ICT

Xu Jiang is a Senior Signal Integrity Engineer at Luxshare-Tech. She reeived her PhD in Microelectronics, Electrical Engineering, University of New Brunswick, Canada. Dr. Jiang has over 10 years of experience in signal integrity of high-speed interconnection and SI/PI of IC chips. Prior to her interests in the high-speed signal integrity, Dr. Jiang has over 15 years of IC designs experience, especially high-speed IO designs, IBIS-AMI modeling and transistor modeling. Over the last decade Dr. Jiang spent her career in HFSS simulation and analysis of IO connectors of OSFP, QSFP-DD, SFP-DD, zQSFP, zSFP, zCXP and GenZ, backplane connectors and board-to-board connectors, PCB board footprint design and analysis, high-speed cable assemblies (passive and active), as well as the channel simulations. Dr. Jiang is an accomplished engineer.