DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.


Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Joungho KimProfessorKorea Advanced Institute of Science and Technology

Joungho Kim (SM’14–F’16) received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree from the University of Michigan, Ann Arbor, MI, USA, in 1993, all in electrical engineering. He joined the Memory Division, Samsung Electronics, Suwon, Korea, in 1994, where he was involved in gigabit-scale DRAM design. In 1996, he joined the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. He is currently a Professor with the Department of Electrical Engineering, KAIST. He is also the Director of the 3-D Integrated Circuit (IC) Research Center supported by SK Hynix Inc., and the Smart Automotive Electronics Research Center supported by KET Inc. He has given more than 219 invited talks and tutorials in academia and related industries. In particular, his major research interests include chip-package-printed circuit board (PCB) co-design and co-simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3-D IC, through- silicon via (TSV), and interposer. He has authored or co-authored over 404 technical papers in refereed journals and conference proceedings. He has authored a book entitled Electrical Design of Through-Silicon-Via (Springer, 2014). His current research interests include electromagnetic compatibility (EMC) modeling, design, and measurement methodologies of 3-D IC, TSV, interposer, system-in-package, multilayer PCB, and wireless power transfer (WPT) technology for 3-D IC. Dr. Kim was a recipient of the Outstanding Academic Achievement Faculty Award of KAIST in 2006, the KAIST Grand Research Award in 2008, the National 100 Best Project Award in 2009, the KAIST International Collaboration Award in 2010, the KAIST Grand Research Award in 2014, respectively, and the Technology Achievement Award from the IEEE Electromagnetic Society in 2010. He was the Conference Chair of the IEEE WPT Conference in Jeju Island, Korea, in 2014, the Symposium Chair of the IEEE Electrical Design of Advanced Packaging and Systems Symposium in 2008, and the TPC Chair of the Asia-Pacific International EMC Symposium in 2011. He was appointed as the IEEE EMC Society Distinguished Lecturer from 2009 to 2011. He is a TPC Member of Electrical Performance of Electronic Packaging and System. He is an Associate Editor of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY. He served as a Guest Editor of the Special Issue of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY for PCB level signal integrity, power integrity, and electromagnetic interference/EMC in 2010, and the Special Issue of the IEEE TRANSACTIONS ON ADVANCED PACKAGING for through-silicon-via in 2011. Recently, he published a book, “Electrical Design of Through Silicon Via,” by Springer in 2014.

Presenting: