designcon is part of the Informa Markets Division of Informa PLC
This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.
April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Stas Litski is a team leader of the Signal and Power Integrity team at Intel Analog Mixed Signal division, responsible for development, design, simulation and measurement of package and boards for validation of next generation Intel HSIOs IPs such as 112Gbps and 224Gbps. He was responsible for design and simulation of validation boards for Thunderbolt 1 and 2 SoCs.