DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.


Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Jun So PakPricipal EngineerSamsung Elecronics Co

Jun So Pak is a principal engineer of Design Technology Team at Foundry Business of Samsung Electronics Co., Ltd. His responsibility includes setting of system level signal integrity (SI) & power integrity (PI) analyses and advising board level SI/PI enhancement methods in the fields of high speed memory interfaces and serial interfaces. He received the M.S, and Ph. D degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2000, and 2005, respectively. He worked as a post doctor at AIST, Tsukuba, Japan from 2005 to 2007, and as a research professor at KAIST from 2007 to 2012. He is an editor of the book, which has a title of 'Electrical Design of Through Silicon Via' and was published in 2014 from Springer. He is the author and co-author of 72 journal and conference papers.

Presenting: