DesignCon 2022 Schedule Builder

Adee Ran is a hardware principal engineer at Cisco systems, working on architecture, analysis and algorithms for high-speed signaling silicon for high-end data center applications. He has joined Cisco in 2021. Prior to Cisco he worked for Intel for 18 years and led architecture, modeling and analysis for PHY and SERDES subsystems in several state-of-the-art high-volume products. Adee is an active member of the IEEE 802.3 Ethernet working group, currently a technical advisor to the editorial team in 802.3ck, and previously the editor of electrical clauses in 802.3by and 802.3cd and a key contributor to many other projects, and was the originator and main driver of COM (Channel Operating Margin) and related specification methodology. Additionally, he has authored several conference papers and was granted more than 30 patents. Adee received his BSc and MSc degrees in electrical engineering from the Technion, Israel institute of technology.

Presenting:

• Validation of Achieving 200Gbps Signaling per Electrical Lane Over 1 Meter of Passive Twinaxial Copper Cable